Positive slack in Synopsys Design Compiler

[always84]

Hello I'm runnign synthesis with Design Compiler. After differents synthesis my results in report timing, says that the slack is zero or negative. So my question is, because i'm looking for positive slack for a secondary power optimization, how can I see the positive slack?

 

[rca]

Normaly, you should have a positive slack before to optimize the design for power.

When the design meet the timing, you can look at the power.

But in general, the synthesis tool has the goal to meet the timing and reduce area/power.

If you didn't meet the timing (or with a very small negative slack) at the synthesis, you can't be able to meet the timing during the place & route. So you need to fix the constraints or the design to meet the timing before continue with the power optimization.

 

[amraldo]

Start with your critical path and try to optimize it by smart coding/logic.
--
Amr

 

[always84]

With optimization constraint and compile options i've obtain a positive slack, or a non negative slack.. But to realize power optimization i've decide to reduce the timing constraint at the first value, without optimization constraint,wich the slack is zero, in this way the compiler can improve power optimization. If i try to make power optimization with strong timig optimizations, and so a little positive slack, my power optimization aren't strong. Is this approch correct? How can i see crtical paths? only in report timig or with design vision (lighted in my schematic)?

 

[rca]

report timing reports you the worst path, and design vision can highligh it in the schematic, at this level, that's didn't provide more information.