positive gate voltage in J-FET

[The Joy of Electronics]

Hi...

As u sure know in the normal mode of the operation of J-FET the gate voltage should be negative. But the device can also function when the gate voltage is positive less than about 0.5 volts where the gate channel diode is not still completely on. Positive voltages in ecess of this value is forbidden since they may damage the device. Now the question is why do such voltages damage the device. Isn't it rite that the gate forms a diode with the channel? Is this diode a particular one?

thanx for ur answers in advance!

 

[ieropsaltic]

Well, I'm not sure about the transistor's damage ,but the basic idea pf the J-FET transistor is modulating the current passing from drain to source by the applied voltage to the gate (in fact, this is the idea of almost all transistors) .This is preformed by variation of the channel's width through which the current passes form drain to source by the depletion region of the reversed PN junction due to the gate voltage (depletion width is proportional to root the voltage) .Ideally, it's required that no current passes from source or drain to the gate .When you apply enough positive voltage to the gate to make the junction forward biased, current can pass directly from the source (drain) to the gate and gate voltage will no longer control the drain-source current ,thus, the J-FET won't function as a transistor .

 

[The Joy of Electronics]

Well, I'm not sure about the transistor's damage ,but the basic idea pf the J-FET transistor is modulating the current passing from drain to source by the applied voltage to the gate (in fact, this is the idea of almost all transistors) .This is preformed by variation of the channel's width through which the current passes form drain to source by the depletion region of the reversed PN junction due to the gate voltage (depletion width is proportional to root the voltage) .Ideally, it's required that no current passes from source or drain to the gate .When you apply enough positive voltage to the gate to make the junction forward biased, current can pass directly from the source (drain) to the gate and gate voltage will no longer control the drain-source current ,thus, the J-FET won't function as a transistor .

Sorry, but I think u forgot the main point of my question.

By the way, as I said before with the gate channel diode slightly forward biased the gate voltage surely controls the drain-source current.

 

[Kral]

The Joy of Electronics,
Gate-Source junctions are tiny. The gate current increases exponentially with voltage. If the current becomes excessive, the temperature in the region of the gate-soruce diode will become high enough to damage the junction.
regards,
Kral

 

[diemilio]

Working a JFET with a positive Vgs won't damage the device, you just need to make sure the power dissipation (Ids*Vds+Igs*Vgs) won't exceed the device's maximun value. Remember that as you keep increasing Vgs, Igs would increase exponentially (cause the junction would be foward biased) making your Power dissipation increase dramatically.

As you should know, RF MESFETs are used with positive Vgs values, and they work just fine. I know that JFETs and MESFETs are physically different, but remember that their electical properties are quite similar.

Hope this helps,

diemilio