positive edge triggered d flip flop

[urimi]

hi friends,

how to design a positive edge triggered d flip flop from the truth table(using transistors)?

Thank you in advance

 

[FvM]

déjà vu https://www.edaboard.com/threads/303562/
No crosspostings!

 

[urimi]

Hi FvM,

whatever u said that is related to digital. i too did like that, but i want in analog. anyway thank you for your reply.

 

[FvM]

whatever u said that is related to digital.

Don't know what you mean. By nature, digital gates are made of transistors. A gate symbol in an ASIC design represents a transistor level macro. I presume that every lecture about digital IC designs starts with an explanation of transistor level implementation. So you shouldn't have a problem to expand the gate level DFF schematics to transistor level.

By the way, you didn't read the links in the previous thread thoroughly. There are transistor level FF schematics as well.