LuigiFassio
Newbie
Hi all,
I'm going crazy in understanding what is poly layer in 180nm TSMC.
From my knowlodge i know is n+ polysilicon. From the DRC error looks like is p+ because the error call the poly as P GATE.
In all the thecnology document i cannot find something that explain all the layer that i can use in the layout. I found one that explain just the common layer.
if I just place a poly square on the psub there will be also the oxide?
thanks a lot for the help
I'm going crazy in understanding what is poly layer in 180nm TSMC.
From my knowlodge i know is n+ polysilicon. From the DRC error looks like is p+ because the error call the poly as P GATE.
In all the thecnology document i cannot find something that explain all the layer that i can use in the layout. I found one that explain just the common layer.
if I just place a poly square on the psub there will be also the oxide?
thanks a lot for the help