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poly layer in TSMC 180nm

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LuigiFassio

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Hi all,

I'm going crazy in understanding what is poly layer in 180nm TSMC.

From my knowlodge i know is n+ polysilicon. From the DRC error looks like is p+ because the error call the poly as P GATE.



In all the thecnology document i cannot find something that explain all the layer that i can use in the layout. I found one that explain just the common layer.



if I just place a poly square on the psub there will be also the oxide?



thanks a lot for the help
Slight smile
 

littlej_zju

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From your description P-gate, you should draw the PMOS layout, right?
In PMOS, poly layer and p+ layer should be overlaped to generate P-gate.
 

timof

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Poly is a layer, like metal layer, made of polysilicon material.
It's used mostly for gates of MOSFETs, both nMOS and pMOS, but also for some other purposes (poly resistors, poly to poly capacitors, etc.).

When deposited, poly layer may be undated, or pre-doped.

But subsequent implantation by n+ (n+ means very heavily doped by donors, making its conductivity n-type), or p+, make it NPOLY and PPOLY.

On top of that poly can be silicided - a metallic material is place on top of poly, and baked into it - making it a very low-resistive material (with sheet rho of the order of 10 Ohm/sq).

You have a mask for poly, and masks for NPLUS (n+) and PPLUS (p+) implants.

NPOLY = POLY AND NPLUS

PPOLY = POLY AND PPLUS

When NPOLY touches PPOLY, there is electrical connections between them.

Also, poly can be drawn over ACTIVE (silicon), or outside (FIELD - from "field isolation").

GPOLY = POLY AND ACTIVE - this is called "gate poly" (can be n+ or p+).

FPOLY = POLY NOT ACTIVE - this is called "field poly".

All this is true not only for 180nm and TSMC, this is a basic thing about (planar) MOSFETs - any fab, any process.

These are so basic, implied things, that technology manuals usually do not describe these basics.
Like books on calculus do not teach you arithmetics or algebra.

MOSFET gates in latest technologies - FinFETs - have a much more complicated construction (but treated very similarly in PDK and in IC design flow).
 

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