POLY in Transistor layout

[Willt]

Hi friends,

I'm a newbie in drawing layout. A simple question: Referring to the attached diagram, why is there a minimum spacing between ACTIVE & POLY?? Is this for keeping the effective width (Weff) equal to the transistor width drawn?? Or for other reasons??

Your comment is highly appreciated ~

Will

 

[Shohdy]

Hi,
This minimum spacing is to gaurantee that the drain and source areas will not be shorted to each other during manufacturing of this device.
In the manufacture steps of this device, the poly is deposited over the subestrate first, next is implanting the substrate with the required diffusion n+ or p+, so if the poly was not fully covering the transistor active area, as shown in figure, a small doped channal will exist between the source and drain areas shorting them to each other.

Hope this helps,

Regards,
Shohdy

 

[Willt]

Hi Shohdy,

I get it now ~ Thanks for your clear explanation ~

Will

 

[NightHawk_099]

Thanks for the image. It makes it easier to understand.

 

[soorajsram]

Shohdy is absolutely right.