[POLL] Program your FPGA?

[OvErFlO]

I use VHDL, I don't understant people that use C or Labview... more abstraction it isn't good, for me.

 

[mobile-it]

I use VHDL, I don't understant people that use C or Labview... more abstraction it isn't good, for me.

That's maybe right that more abstraction isn't good but maybe in an economic point of view you may want to use LabVIEW for it's simple way in programming a real-time FPGA system?

 

[mobile-it]

Are there any people here on this forum using LabVIEW FPGA?

I am working with this and also trying to use the Libero Actel design flow for programming FPGA's and I must say I like them both!!!

 

[salma ali bakr]

i use VHDL and verilog
but i prefer VHDL cause it is strongly typed
and it is easier to deal with (for me at least)
verilog is closer to C and i hate C unfortunately

so what about the labview debate
anyone got info about that
we'd like to benefit

 

[mobile-it]

The problem with LabVIEW FPGA is that it is a whole other concept; you have to program with icons (graphical programming)
The advantage of using LabVIEW is that you can quickly design a system and test it; It is more and "high-level" programming language where the engineers (not programmers) work with. They analyse a solution with a designflow and this designflow can be integrated by icons in LabVIEW.


The problem with LabVIEW FPGA is that it only support National Instruments hardware (Xilinx Virtex II inside).

If you can port LabVIEW FPGA to a version where you can see the VHDL code that is generated by LabVIEW FPGA and then Port this VHDL code to Altera/Actel/... you will be rich


At the moment I am experimenting with a LabVIEW compactrio System (https://www.ni.com/compactrio)

also check https://www.ni.com/fpga

 

[moh_monem43]

i use VHDL because i started with it.

 

[cdcll]

The problem with LabVIEW FPGA is that it is a whole other concept; you have to program with icons (graphical programming)
The advantage of using LabVIEW is that you can quickly design a system and test it; It is more and "high-level" programming language where the engineers (not programmers) work with. They analyse a solution with a designflow and this designflow can be integrated by icons in LabVIEW.


The problem with LabVIEW FPGA is that it only support National Instruments hardware (Xilinx Virtex II inside).

If you can port LabVIEW FPGA to a version where you can see the VHDL code that is generated by LabVIEW FPGA and then Port this VHDL code to @ltera/Actel/... you will be rich


At the moment I am experimenting with a LabVIEW compactrio System (h**p://www.ni.com/compactrio)

also check h**p://www.ni.com/fpga

sounds very interesting!

 

[viking84red]

VHDL and verilog are the best

 

[pahol]

VHDL or VerilogHDL are best for now. But in future (I cannot expect when) may be C or SystemC.

 

[chviswanadh]

I use verilog and VHDL for the FPGA programming.
how about system c and system verilog

 

[howz]

i prefer to use schematic and VhDL together. i normally use schematic tools to implement the low level design and use vhdl for the top level module.

 

[dunets]

Hi!
Tools and language usage depends of design's starting point. For most designs the VHDL or Verilog is enough. But, if design starts from high-level, then HDL only language usage is not convenient. We have to use also different tools (and languages):
* If starting point is Matlab, you can try to use Model based design (Synplify DSP, Mathworks HDL Coder, Xilinx System Generator, Altera DSP Builder). Matlab (Simulink) has “Link for ModelSim” Component, which allows co-simulating in Simulink HDL project. Such technique can be used for testbench creation.
* If starting point is SystemC (incl. C++) you can try automatically generate HDL code using tools from Celoxica (DK Design Suite), Forte (Cynthesizer) and Mentor (CatapultC).

 

[mobile-it]

Hi!
Tools and language usage depends of design's starting point. For most designs the VHDL or Verilog is enough. But, if design starts from high-level, then HDL only language usage is not convenient. We have to use also different tools (and languages):
* If starting point is Matlab, you can try to use Model based design (Synplify DSP, Mathworks HDL Coder, Xilinx System Generator, @ltera DSP Builder). Matlab (Simulink) has “Link for ModelSim” Component, which allows co-simulating in Simulink HDL project. Such technique can be used for testbench creation.
* If starting point is SystemC (incl. C++) you can try automatically generate HDL code using tools from Celoxica (DK Design Suite), Forte (Cynthesizer) and Mentor (CatapultC).

Is there a free tool to synthesize SystemC to your FPGA (Xilinx or Actel)?

 

[dunets]

Is there a free tool to synthesize SystemC to your FPGA (Xilinx or Actel)?

As i know, where are not free tool to synthesize SystemC to your FPGA (Xilinx or Actel)?

 

[salma ali bakr]

hi dunets,

can u please explain this more:

Matlab (Simulink) has “Link for ModelSim” Component, which allows co-simulating in Simulink HDL project. Such technique can be used for testbench creation.

thanks in advance,
Salma

 

[yasser_shoukry]

I use veriolg as i learnt it while i was having an internship in Mentor Graphics Egypt for 2 month and i had to implement some hardware modules to complete my design.

Before that internship i was using VHDL but after using verilog i really become a verilog fan

 

[dunets]

hi dunets,

can u please explain this more:

Matlab (Simulink) has “Link for ModelSim” Component, which allows co-simulating in Simulink HDL project. Such technique can be used for testbench creation.

thanks in advance,
Salma

Hi!
More information about it you can find here:

h**p://www.mathworks.com/access/helpdesk/help/toolbox/modelsim/a1041536902.html

Sincerely, dunets

 

[JohnJ]

I am just catching up with HDL. I worked on debugging a Supercomputer prototype circa 1985. At that time we used PALs for the instruction decoder and programmed them using those schematics and dots and hand assembled the programming files.

To me HDL is too much abstration, but with the size of today's chips?? If you take VHDL code and remove the logic equation and the required pins from the code you still have 80% of the code left! This to me is overhead! I can't imagine what a processor element that took 50 pages of schematic would look like in HDL.

I don't think that any current HDL simplifies anything.

All this being said, I am slowly but surely learning VHDL, because that's what the industry is using. Ya' can't fight progress. :!:

 

[mobile-it]

At this time there is I think much going on in the FPGA domain; much people are working on PSOC systems where you collect your IP's written by other people and then you build your own HW platform where then you program the software on in C language... For the parallel blocks you only have to work with VHDL.

Even an OS (uClinux,...) is quite often installed on a PSOC system.

 

[phdang]

I use Coware SPW for block-oriented design; after verifying the operation of the system, SPW will generate to VHDL. Manually pinout in Xilinx ISE and/or EDK. This workflow is easier for me than purely programing in VHDL.