OvErFlO said:I use VHDL, I don't understant people that use C or Labview... more abstraction it isn't good, for me.
mobile-it said:The problem with LabVIEW FPGA is that it is a whole other concept; you have to program with icons (graphical programming)
The advantage of using LabVIEW is that you can quickly design a system and test it; It is more and "high-level" programming language where the engineers (not programmers) work with. They analyse a solution with a designflow and this designflow can be integrated by icons in LabVIEW.
The problem with LabVIEW FPGA is that it only support National Instruments hardware (Xilinx Virtex II inside).
If you can port LabVIEW FPGA to a version where you can see the VHDL code that is generated by LabVIEW FPGA and then Port this VHDL code to @ltera/Actel/... you will be rich
At the moment I am experimenting with a LabVIEW compactrio System (h**p://www.ni.com/compactrio)
also check h**p://www.ni.com/fpga
Tools and language usage depends of design's starting point. For most designs the VHDL or Verilog is enough. But, if design starts from high-level, then HDL only language usage is not convenient. We have to use also different tools (and languages):
* If starting point is Matlab, you can try to use Model based design (Synplify DSP, Mathworks HDL Coder, Xilinx System Generator, @ltera DSP Builder). Matlab (Simulink) has “Link for ModelSim” Component, which allows co-simulating in Simulink HDL project. Such technique can be used for testbench creation.
* If starting point is SystemC (incl. C++) you can try automatically generate HDL code using tools from Celoxica (DK Design Suite), Forte (Cynthesizer) and Mentor (CatapultC).
Is there a free tool to synthesize SystemC to your FPGA (Xilinx or Actel)?
salma ali bakr said:hi dunets,
can u please explain this more:
Matlab (Simulink) has “Link for ModelSim” Component, which allows co-simulating in Simulink HDL project. Such technique can be used for testbench creation.
thanks in advance,