plz remove the error arrise in comparator program in hspice.

[sandeep pagare]

this is the code of comparator( which shown below). this arrise error ( end card missing at reading). how can remove this error plz suggest me.



****comparator*******
.options nomod node list brief POST ingold=1
.option scale=1u
.global control
.param pvdd=5

*****Power Supply********
VDD VDD 0 DC 5
Vp vp 0 DC 2.5 PULSE 2.46 2.54 0n 0 0 10n 20n
vm vm 0 DC 2.5
vss vss 0 dc 2.5v
vbiasn vss 0 20uA

M1 n1 vp vss 0 nch L=1 W=10
M2 n2 vm vss 0 nch L=1 W=10
Ma vss vbiasn 0 0 nch L=2 W=20
M31 n1 n1 vdd vdd pch L=1 W=20
M41 n2 n2 vdd vdd pch L=1 W=20
M3 vop n1 vdd vdd pch L=1 W=20
M4 vom n2 vdd vdd pch L=1 W=20
M5 vop vop vc 0 nch L=1 W=10
M6 vop vom vc 0 nch L=1 W=10
M7 vom vop vc 0 nch L=1 W=10
M8 vom vom vc 0 nch L=1 W=10
Mb vc vc 0 0 nch L=10 W=10
M9L n4 vom n3 0 nch L=1 W=10
M9R vdo vop n3 0 nch L=1 W=10
M10L n4 n4 vdd vdd pch L=1 W=20
M10R vdo n4 vdd vdd pch L=1 W=20
Mc n3 n4 0 0 nch L=1 W=10
MIN out vdo 0 0 nch L=1 W=10
MIP out vdo vdd vdd pch L=1 W=20
.subckt bias vbiasn vbiasp VDD
M1 Vbiasn Vbiasn 0 0 nch L=2 W=10
M2 Vbiasp Vbiasn Vr 0 nch L=2 W=40
M3 Vbiasn Vbiasp VDD VDD pch L=2 W=30
M4 Vbiasp Vbiasp VDD VDD pch L=2 W=30
Rbias Vr 0 6.5k
MSU1 Vsur Vbiasn 0 0 nch L=2 W=10
MSU2 Vsur Vsur VDD VDD pch L=100 W=10
MSU3 Vbiasp Vsur Vbiasn 0 nch L=1 W=10


******TRANSIENT*******
.tran 100p 150n
.print tran vp vm

.meas max_power max power
.measure TRAN risetime TRIG v(out) VAL='0.1*pvdd' rise=1 TARG V(out) VAL='0.9*pvdd' rise=1
.measure TRAN falltime TRIG v(out) VAL='0.9*pvdd' fall=1 TARG V(out) VAL='0.1*pvdd' fall=1

.lib 'E:\Spice_example\tsmccl013g_logic.spice' TT
.end
.include .\1um_models.txt
.end