PLZ HELP ME OUT IN CLOCK TREE SYNTHESIS==ASTRO===

[jagannathkb]

HI all,
am doing my Mtech project in ASIC design, in back end design after placement when i did clock tree synthesis its not executing its showing some errors saying ===== bout_reg[0]: CP is an implicit ignore pin since is a an non-clock pin==== wat is the reason for this message N how to debug this.....how to give it as sync PIN

thanks

mail me .....jagannath.nitc@gmail.com[/b]

 

[p_shinde]

check ur sdc file, seems u have given wrong root pin or that is a stop pin which would be given in ur sdc.