[SOLVED] Plssss tell me the Error in the vhdl code

[shiny1]

I am trying to store data in the memory vector using the following vhdl code:
But a,m getting following error for quite some days .. Any help pls
ERROR:HDLParsers:808 - "D can not have such operands in this context." D here is the function
ERROR:HDLParsers:164 - parse error, unexpected IDENTIFIER, expecting PIPE or ROW

entity memy is
Port(
     Da   : in std_logic_vector (0 to 0) ;
    adrss  : in std_logic_vector(15 downto 0) := "UUUUUUUUUUUUUUUU" ;  
    Dataoutput : out std_logic  (15 downto 0)
	   );
end LUTmemory;

function D (p: std_logic;
                    RAm : std_logic_vector (0 downto 0))  return std_logic_vector is 
begin 
case p is 
         when '0' => return "1";
          when '1' => return "0";
  when others => return "U";
;
 end case;
 end D;

type ram_type is array (0 to 15) of std_logic_vector(0 to 0) ;
signal mem : ram_type; --:=
 --{"U","U","U","U","U","U","U","U","U","U","U","U","U","U","U","U"};


begin

process 

begin
case Adrss is

 when "1000000000000000" => mem(0)  <= d(da,mem(0)) ;-- the error is here in the assignments
 when "0100000000000000" => mem(1) <=d(da,mem(1)) ;  -- continues till 15
 when "0000000000000001" => mem(15) <= d(da,mem(15)) ;
 when others 
          mem <= mem;
 end case;

Dataoutput <= mem;
 wait on Adrss,mem,da;
end process;

 

[TrickyDicky]

da is a std_logic_vector, but the paramater p to the function is a std_logic. try: d( da(0), mem );

PS. What are you trying to do with this code?
NOTE1. There are syntax errors:
entity labels dont match.
There is no architecture.