pls kindly help me about the working principle of this control circuit for DC-DC?

[zhangyunwu5555]

there is no EA in the LOOP and the feedback voltage is directly given to the COMP, and the chip can be used in BUCK , BOOST AND buck-boost
after analysis I just find out : the working frequency is fixed by clock, and the duty is determined by the Vfb and Vref during one cycle，and i want to know what is the control method it named and its advantages or drawbacks

 

[checkmate]

The general term you are looking for is "current mode control".
This is opposed to "voltage mode control".
Have fun googling

 

[KerimF]

Hi,

I guess when you will analyse it, you will likely find out its limits.
For example, the maximum duty cycle of the main switch is equal to the duty cycle of the clock at the AND input.
The circuit is for a 7.5V regulator (supply).

Kerim

 

[zhangyunwu5555]

Hi Kerim:

thx for your minding.Just like you say "the the maximum duty cycle of the main switch is equal to the duty cycle of the clock at the AND input"
and after simulation i find out the duty at the AND input is discontinuous in a cycle, changing with the ripple of Vout,
so can you tell me why design it like this?
Best wishes

jimmy

 

[KerimF]

Hi Jimmy,

Actually, every engineer designs what could be best relative to him and I am afraid that this depends on too many factors.
In any case and with time, added solutions of the same basic problem are continuously presented from different sources.
On my side, when I need designing a board for a new application (usually defined by the user or the new market), I don't follow exactly any other's solution so I always end up with new topologies which, I believe, are suitable for my users only and not the world; in term of reliability, component availability and cost.

My point is that it is good for one analyzing a circuit to learn something from it. But searching the reasons for which an engineer has applied it may not be necessary. I think the important questions could be:

Is it good for me or not?
If not, how could I update it for my need?

For instance, since I cannot find/buy easily the main components of SMPS (mainly Schottky diodes and power ferrite cores) and the ready-made supplies became not pricey, I didn’t try designing any model of it yet. I just add a ready-made type in my new products when necessary.

Wish you good luck,

Kerim

 

[FvM]

The schematic doesn't show any kind of current sensing, thus it won't be normally considered as current mode. A similar design - with an additional peak current detector controlling the oscillator - can be found in 78S40 and MC34063. It's not classical current mode however.

The operation principle can be probably named clocked on-off control or something like that. I'm not aware of a commonly used name for it. The circuit i ssimple but doesn't show stable stationary waveforms like a pwm controller. Output ripple will be usually higher.

 

[zhangyunwu5555]

Hi kerim:

Thanks for your advising very much!

Jimmy

---------- Post added at 02:48 ---------- Previous post was at 02:39 ----------



---------- Post added at 02:50 ---------- Previous post was at 02:48 ----------

Hi Fvm:

What do you mean " an additional peak current detector controlling the oscillator", can you describe it in detail which I failed to find in the datasheet of 78S40 or 34063?
And just as you say the circuit I post here is just triggered on by the Clock, after that, the main switch is controlled by compared results of Vfb and Vref. and you're right that the output ripple is higher, and can you give some advice to reduce it by adding some blocks in the posted circuit?

Best wishes
Jimmy

 

[FvM]

If you have a 34063 datasheet, you surely noticed that the standard application circuit uses a current sense resistor and a threshold voltage for the peak current detector is specified. In so far, the design is different from the schematic in post #1. The remaining circuit has the same structure. There's an application note discussing MC34063 operation. https://www.onsemi.com/pub/Collateral/AN920-D.PDF

In my view, limited performance of this simple control structure should be taken as a fact. The on-off pulse pattern and respective output ripple is somewhat chaotic and can't be easily predicted. But it can be influenced by many circuit parameters, e.g. inductance, capacitor ESR, oscillator frequency, additional feedback frequency compensation, curren limiting means.

 

[zhangyunwu5555]

thx a lot！