C , VERILOG, VHDL.

[krisdan]

Can anyone help me with the vhdl code for a 4-bit parallel access shift registers with its test bench?
Please i really need your urgent reply.

 

[nick123]

hey i helped u already!!

 

[nick123]

LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------------
ENTITY shiftreg4 IS
PORT ( P: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Clock:IN STD_LOGIC;
LOAD,I:IN STD_LOGIC;
Q:BUFFER IN STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END shiftreg4;
------------------------------------------------
ARCHITECTURE arch OF shiftreg4 IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'event AND Clock='1';
IF LOAD='1' THEN
Q<=P;
ELSE
Q(0)<=Q(1);
Q(1)<=Q(2);
Q(2)<=Q(3);
Q(3)<=I;
END IF
END PROCESS;
END ARCH;
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