PLL's jitter, stability, etc according to it's BW

[Sadegh.j]

PLL BW, jitter etc

Hi all

What is the relation ship between the PLL BW and its
1) output jitter
2) lock time
3) Stability

Thanks

Any reference would be appreciated

 

[mengcy]

PLL BW, jitter etc

you can sweep the bandwidth with PLL design assitant.
the result may appear.

 

[sunbeam]

PLL BW, jitter etc

It depends on...
There are some parameters which influence the performance you have said.
jitter: if your system's noise mainly from vco, then a larger BW helps to reduce the jitter; the setting of BW is a trade-off with the vco phase noise and the reference noise(divider noise or sdm quantization noise, etc)

Lock time: lock time is inversely proportional to the BW and damping factor.

Stability: Roughly, the larger BW, the poor stability...

the tool "PLL design asistant" mengcy mentioned above is a very good PLL behavior simulation tool.
you can find it from Dr.Perrott's group.