Hi fred23,
Thanks for suggesting adisimpll to simulate reference spurs by
accounting opamp bias current.
I am practically observing op amp bias current 3-4mA.
And spurs are as high as -10Bc.
If I consider this bias current in adisimpll ,it gives spur level 60dBc,
Where as phase noise is -104dBc/Hz at Fpd.
What will be absolute spur level than? Phase noise (dBc)+spur level (dBc)
what best can be done in this case? Should I change my opamp to op27
for better noise performance? I am using general purpose LM118
righ now.
I am using the differential topology as the PLL chip provides up and down
outputs separately ,see figure.