PLL with multipel outputs ?

[manish12]

a work come to "Design the pll for multiple outputs "
From where i get theory behind it, or is this concepts exits ?
thanks

 

[vandelay]

Maybe it's a trick question, prompting you to put a clock divisor on the PLL output? The PLL would still only output a single frequency ofcourse.. I cannot see how a single PLL can lock onto multiple frequencies. "Multiple outputs" could perhaps also refer to buffering of the PLL output, in order to drive multiple sinks?

 

[amarnath]

i think you are being asked to design a frequency synthesizer which can output multiple output frequencies based on the ratio of the feedback divider.


amarnath