PLL-Synthesizer Problem

[ElTono]

Hi,

I am working on a project with a PLL synthesizer for an FM receiver. There occurred following problem:

For the receiver, the phase noise at a distance of 20 kHz to the carrier is the most important parameter to comply with certain guidelines. This area is dominated (with correct dimensions of the loop filter) only by the VCO (channel spacing 20 kHz). Can the phase noise be minimized in this area without changing the VCO?

 

[SSA@A]

Can you adjust the loop bandwidth of PLL?

Just FYI.
For your PLL development and evaluation.
"Boosting PLL Design Efficiency From free-running VCO characterizations to closed-loop PLL evaluations"
**broken link removed**

Here's the product web-site that introduced on above application note.
**broken link removed**