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PLL/Synthesizer Design in mm-wave

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go_horns

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Hi all, after some reading, most of the recent literature on mm-wave PLL have focused on circuit techniques that may either extend the VCO tuning range, reduce PFD spurs, and so on. While they have been helpful, I want to ask if there is significant or key elements in mm-wave PLL design on the system/architectural level that is different from conventional design at lower frequencies?

Most of the paper don't really tell you how they have arrived at the architectural choice of a type-II, 3rd order charge pump (I mean in mm-wave literature), so it gives me the impression that all the important stuff is at the transistor level, whereas system design approach is similar to before.

Stability issues? reference frequency choice (divider ratio?) parasitics at mm-wave? etc....

Thanks!
 

biff44

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The only differences between a mmw design and a 2 Ghz PLL center around the following facts:

1) you can not readily get a digital divider to divide the frequency down to a lower level
2) the higher the frequency, the more the phase noise of the crystal reference clock and the associated low frequency digital circuitry cause trouble. This is because effective phase noise goes up as 20 Log N, where N is the difference between your output frequency and the clock frequency. This tends to drive the architecture.
3) oscillator Q will be pretty bad due to the high frequency and limited varactor diode Q
 

WimRFP

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Hello,

One option is to make a very stable fixed frequency source and use a harmonic mixer to down-convert the mm-wave signal of interest to a frequency where it can be processed with standard PLL circuits.

The spikes to drive a sample mixer can be generated with SRD or other non-linear components. The advantage is that the PLL noise is not increased, as there is no division ratio (the mixer provides a frequency offset only). The disadvantage is that your mm-wave source must be around the desired frequency as these systems lock around the harmonics produced by the mixer.
 

biff44

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WimRFP said:
Hello,

The advantage is that the PLL noise is not increased, as there is no division ratio (the mixer provides a frequency offset only). .

Guess again!
 

biff44

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using a sampler as a mixer does not improve the 20 Log N phase noise. The reason is depicted attached.

But it is even worse than that. The sampler will have a poor conversion loss and a limited compression point, so your far from the carrier noise floor will be poor (if you try to use a high loop bandwidth).

Also, because of aliasing, you will be sampling the thermal noise at all of the sidebands +/- the SRD spikes. ie. if your SRD is driven by a 1 GHz source, and you are trying to sample a 40.1 GHz signal, your sampler will output a 100 MHz that is a composite of all signals: 1.9, 2.1, 2.9, 3.1....39.9, 40.1, 40.9..... so there will be a lot of added noise. You would have to do some fancy antialiasing BANDPASS filtering and 40 GHz LNA work to overcome that.

Never the less, you are right. There are a lot of Phase Locked DRO oscillators that work this way. They get away with it by using a narrow loop bandwidth and having a high Q fixed oscillator. Tunable PLLs will be more challenging.
 

WimRFP

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Hello,

You are right that because of the high conversion loss of sampling mixers at high harmonic numbers, the output signal to noise ratio reduces and that this noise has a phase noise component. So you need at least a good input signal to noise ratio and a good mixer/IF/LO combination.

One can reduce the harmonic number by using a higher frequency (or adding a multiplying stage before the mixer to increase the LO frequency [and its phase noise]). A down conversion process, keeps the phase relation, so the phase noise of your PLL is not multiplied with the division number.

Before making a final decision for any frequency source, one has to evaluate all relevant noise contributions.
 

biff44

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WimRFP said:
Hello,



One can reduce the harmonic number by using a higher frequency (or adding a multiplying stage before the mixer to increase the LO frequency [and its phase noise]). A down conversion process, keeps the phase relation, so the phase noise of your PLL is not multiplied with the division number.

.

Well, I don't know what else to tell you, except that you are simply wrong. It does not matter if you use a fundamental mixer run off of a XN frequency multipler, or use an SRD and a phase sampler witht he same XN ratio between the clock and the effective LO frequency, the phase noise degradation in either case is 20 Log N. Go make a measurement if you are so sure. I have made hundreds.
 

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Hello,

I was thinking of the setup given in the image.



VCO frequency >> input frequency to divider
 

biff44

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Yep, that is what I thought you were saying. Do you agree that in the below two block diagrams, the IF outputs from the two mixers both have +/- 40 dgrees of phase modulation on them? (assuming the 40.1 and 1 Ghz sources to be ideal/noisless).
 

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Hello,

Drawing fully clear, and also the noise analysis for the very stable source.

Probably we had some misunderstanding

In my posting I was referring the PLL part (so reference, phase comparator, divider).

By using the offset PLL, the divider can be a simple UHF one. When sufficient S/N ratio, phase noise at VCO output will be phase noise at divider input + phase noise of K*(phase noise of stable source).

K = harmonic number in case of harmonic mixing.

As long as the relative phase noise of the stable source (phase noise / Fcenter) is better then that of the PLL (referenced to frequency at divider input), this scheme has some benefit.

When you skip the whole offset mixer, you need a large N in the divider, increasing the noise from the PLL.
 

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Good! Glad we are on the same page. If there were some way to circumvent the 20 Log N noise, I would love to hear of it. But I have thought long and hard over the years, and have not found a way.

I agree, an offset PLL, or maybe multiple loops, would be the best way to go for low noise. Also, mixing in a DDS output in one of the offset LO's could get you good phase noise with very small step size.
 

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