PLL synthesizer and VCO tuning voltage range

[dumindu89]

VCO of the PLL synthesizer has a limited range of tuning voltage (let's say 0V to 3V) . So how I achieve only these tuning range with proportional to the count of the divider (let's say , maximum count of the divider gives you the maximum frequency of the locked range)?

Can I achieve this using a proper low pass filter as the loop filter?
If yes, what things should I consider?

 

[biff44]

maybe you could rephrase your question, as it does not make any sense to me.

If you have a vco that has a tuning range of 0 to 3 volts, and you connect it to a modern PLL chip with a charge pump output, with that PLL chip running off of say 3.3 V DC, then the PLL phase detector will automatically put out a voltage between zero and 3 volts to try to lock up the VCO. You DO need a loop filter between the phase detector output and the VCO tune input because the control loop gain and phase shift vs. frequency needs to be set to make the control loop stable.

 

[Zottel]

You have a PLL-Chip with VCO inside?

 

[dumindu89]

You have a PLL-Chip with VCO inside?

No.
I have to design the PLL seperately.

 

[tony_lth]

Use Analog Device free software AdiSimPLL to design the PLL circuits.
That's the most successful software to do so.

 

[RCinFLA]

There is a lot of details in a synthesizer design. Actual useable range of VCO have more factors then just the total tuning spread of the VCO and the sythesizer's divider range. Kvco is an important factor in loop stability and generally unless special techniques are used to compensate for the non-uniform frequency MHz/volt of tuning range the loop with get into stability trouble some point in the tuning range.

Many designs bandsplit the VCO in steps to keep the Kvco more constant. You also have the divider ratio within the loop that changes the total loop gain.