coolstuff07
Advanced Member level 4
Hello All,
Iam designing PLL with input frequency 2-5MHz and output frequency of 50-100MHz, my question is what should be the steady state phase error [Dead Zone] value at PHFD?
Is there any relationship between phase error and operating frequency.
Bye.
Iam designing PLL with input frequency 2-5MHz and output frequency of 50-100MHz, my question is what should be the steady state phase error [Dead Zone] value at PHFD?
Is there any relationship between phase error and operating frequency.
Bye.