PLL steady state Phase error

[coolstuff07]

Hello All,

Iam designing PLL with input frequency 2-5MHz and output frequency of 50-100MHz, my question is what should be the steady state phase error [Dead Zone] value at PHFD?

Is there any relationship between phase error and operating frequency.

Bye.

 

[FvM]

I would expect zero steady state error for all frequencies.

 

[coolstuff07]

Hi,

Can you please further elaborate?

I feel there is a need of minimum static phase error to pump current current from charge pump during lock condition.

My Questions does static phase error is i/p, o/p frequency dependent or not.

Bye.

 

[biff44]

If there is a dead zone, then there can in-fact be a phase error. I would think of it more as a phase noise term, rather than an error, since the VCO will be moving around slightly due to random noise. If you can stand slightly higher clock spurs, you can apply a bias so that the phase detector stays out of the dead zone when locked.

This assumes you have at least a type 2 control loop (where there is an integrating element somewhere). If there is not integrator, then you can have a quite large phase error, depending on your open loop DC gain.

 

[dick_freebird]

There will always be a net leakage from your charge pump, and this will have
to be overcome by some pumping hence some phase offset to induce it. In
some cases the leakage of a technology is enough of a problem that people
go to an up/down digital output instead, requiring a slightly more complicated
loop amp scheme (which itself probably has an offset voltage and VOUT/AVOL
errors, still needing a finite phase error to skew the up and down output
activity to balance.

Look at quantifying these kinds of things, work the math and maybe you'll
see what you're looking for.