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PLL phase noise profile

Matmat45750

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Hello everyone,

I am designing my first PLL.

The input clock will be around 32.786 kHz and the VCO's free running frequency is at 32.786 kHz. I am currently trying to estimate the VCO's and input clock's phase noise to set the optimized bandwidth and then get the minimum output jitter.

I have studied many PLL's phase noise profile and most of them look like this one:

pll-phase-noise.JPG




I have understood that the frequency offset is (in my case) Foffset = Real_frequency - 32.786 kHz (carrier_frequency)

Then taking a look to this plot I understand that F_loop (PLL Bandwidth) is higher than the carrier frequency, but I have also read than 1/20*carrier_frequency < F_loop < 1/10*carrier_frequency.

So I don't understand anymore.

Furthermore, why don't we interest to frequencies between 0 and F_carrier ? Do we consider that the phase noise profile is symmetric ? It would be weird because for each PLL's component the output phase noise is Sout = Sin*H^2

with : - Sout: the phase noise at the PLL's output due to the component (PFD or VCO or Input clock ...)

- Sin: The phase noise due to the component (PFD or VCO or Input clock ...)

- H: The transfer function from the component's input to the PLL's output

And H is either a low (Input clock) or a high (VCO) pass filter, then it is not symmetric.

Thank you very much to all of you.
 

dick_freebird

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In a system you will be very interested in "frequencies between 0
and F_carrier" because low frequencies mixing with carrier, fall
in-band for whatever channel you're trying to occupy and can
break the "mask". "Close-in phase noise".

I have never heard of anyone using a loop filter higher than the
carrier frequency ("carrier" being the VCO output, I would expect)
- because what, then, could you possibly be "filtering"?

You back loop corner off by a factor of 10 or more, just to give
the loop filter some room to attenuate output tone from the
feedback and keep it from "singing to itself". I believe the
"1/20 < Floop < 1/10" is sort of "rule-of-thumb-y", regarding
how "sporty" you can make the loop without getting into
weirdness.
 

Matmat45750

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Thank you for your answer.

Then if we are very interested in frequency between 0 and F_carrier, why do we only look at frequencies higher than F_carrier (cf the figure in my post) ?

Best
 

BigBoss

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For your case only ;

Loop Filter Bandwidth depends also on Lock Time.
Loop Filter is essentially design regarding to Phase Noise Requirements. How much Phase Noise@Offset Frequency will be required and Lock Time will maximally be what
Under all those circumstances, Loop Filter is Designed and a compromise is found. There is no such rule of thumb as you said.
 

arthorios

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The plot you show is the phase noise profile of the PLL output and is symmetric around the carrier. To get to the phase noise contribution of each block in the PLL presented in the plot, we have to assume that the PLL is a continuous-time (CT) system. However, it is actually a discrete-time system since you basically sample the input clock at each transition. So, for the CT approximation to hold, your loop bandwidth must be smaller (<1/10th) than the input frequency.
 

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