PLL Phase Noise Analysis

[4Ceesuns]

When doing a PLL Phase noise analysis, I know reference noise within the loop BW is enhanced 20 log N, but in a digital PLL with a PFD, when the mfg supplies the noise floor or figure of merit, is the PN within the loop BW (enhanced) simply added to the phase detector noise, or is the phase detector noise also enhanced by 20*log N? Thanks in advance.
4Ceesuns

 

[biff44]

since the phase detector is running on some very low frequency, and the divider chain makes the oscillator track any tiny phase jump at the detector but making it N times bigger at the VCO output, yes the phase noise floor of the digital detector gets multiplied by 20 Log N