PLL (phase locked loop) loop bandwidth

[pankajpc]

if one wants to measure pll loop bandwidth of type 2 PLL in spice how do i do that. Actually, the LPF has a R1 and C1 and another smoothing capacitor C2 , 1/10th of C1.

Typically, because of C2, R1, C1 and VCO we will have 3 poles and a zero.

 

[betwixt]

The answer is obviously one of two things:

1. C5 which has half the pole of C4, meaning it can only fly at half mast, or R7 is the wrong polarity.
2. You forgot to tell us which schematic you are referring to.

Brian.

 

[D.A.(Tony)Stewart]

In the linear tracking mode, you can frequency modulate the signal with a sine wave and measure the loop response to determine the -3dB point.

Loop gain and obviously the VCO gain and range in particular influences the -3dB bandwidth set by just the LPF's but since phase error is limited and non-linear beyond the type II range, this will also affect the BW as well and any dividers to multiply the VCO. So each part of the loop has an effect on capture time as well as linear BW.

 

[pankajpc]

So what you mean is to give a sine wave at the reference input and look at the vco o/p. Actually, two pole pll does not depend on damping, however 3d order PLL because of smoothing capacitor C2 is actually 3 pole system which is dependent on damping.

Can you please walk me through the test bench needed for the same in spice/cadence spectre.

thanks
PS: If you are aware of any documentation, paper etc, thesis that talks about PLL loop bandwidth would be of great help.