PLL maximum and minimum input reference frequency

[lipkai]

What defines the maximum and minimum input frequency of the PLL?
Is it the VCO tuning range or loop bandwidth or something else?

I read this somewhere (can't remember the exact source):
"The use of higher reference frequency (Fr) offers an opportunity to widen loop bandwidth and achieve significant improvement in switching speed due to faster phase detector frequencies."

I can understand widening the loop bandwidth will increase the switching speed but does having a fast phase detector frequencies have anything to do with the switching speed? Assuming we have a PLL with the same loop bandwidth, does increasing the reference frequency result in faster switching time?

Thanks.

 

[mengcy]

if the divide ratio is integer,the reference frequency must be divided by the output frequency.
otherwise,we use the possible maximum reference frequency for better phase noise performance.
Switching time is decided by:loop bandwidth ,the damping factor, the frequency deviration.it doesn't matter with reference frequency.

if you have larger reference frequency, you can set a large bandwidth,so you can get faster switching.

 

[lipkai]

Thanks.

 

[Sadegh.j]

Hi

yes, Imagine your frequency is 1GHz, your period would be 1ns and in 10ns, the input chances 10 times, giving the PD, lets say, 10 chances of fix the VCO frequency. Now increase your input frequency to 10 Ghz, your period is 100ps, and in 10ns, the input chances 100 times, giving the PD 100 chances of fix the VCO frequency.

Hope it helps!

 

[ashwinvl]

Mere increase in pfd freq doesnt affect the response of PLL.. As higher pfd freq gives you room for increasing the bandwidth(Wn), increase in B.W leads to a faster response.