PLL locking takes long time, strange frequency vs time curve

[golohoyeah]

Hi, all,
I have a problem of having a strange frequency vs time curves as the image (Cadence simulation with real device). It seems there are steps in between and make the locking time much longer.
Could anyone tell me what is the problem? is it due to the dead zone for the phase detector or what?

thanks in advance.

golohoyeah

 

[FvM]

Could anyone tell me what is the problem? is it due to the dead zone for the phase detector?

If you designed a detector with dead zone, apparently yes. Why did you?

 

[golohoyeah]

I modified an old design which operates at much lower frequency, vco freq. 16MHz; I think I overlook this design paramter.
Do you have any literature for designing phase detector for higher frequency? thanks in advance