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PLL Design Steps (25 Points)

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sky_hit said:
is that it no other information about PLL in VHDL code?


Are you planning to design a ADPLL ?
 

Re: PLL Design Steps

master_picengineer said:
Thanks mouzid,
I'll give 25 point for an practical exemple.

Added after 10 minutes:

Dear mouzid, can you tell me how for a X Mhz input and Y Mhz output PLL ?
(obviously Y >X)

Hi, what if Y<X..how do i use a PLL to do that. I need the PLL to design frequencies both lesser and greater than the reference frequency.
 

I posted the frequency synthesizer design course at this link:
#1039631

Very helpful in designing PLLs.
 

esoteric1 said:
I posted the frequency synthesizer design course at this link:
#1039631

Very helpful in designing PLLs.
As far as I know there is a flow to follow and that depend on the kind of PLL you wanna do.
 

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