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PLL Design Specification

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Sep 3, 2007
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design specification for digital pll

Hi all,
I'm invited to write a specification to a PLL to be used in an appplication (Parallel to serial bits converter). There are many posts & books in this forum on pll design however there is no methodologie in teaching the PLL design technique. When I read a doc/book there is always a lack of something that oblige me to jump to another doc/book to find this information and so on. I lost time and I feel locked in a loop and work is in a blocked phase. That's a PLL, I am in a PLL !
Could you please reply to these questions:

1- What are the parameters that I should/must mension in the specification (apart the frequency obviously). I know that these parameters depends on the application itself.
2- According to what we can choise the order of the PLL.

If anyone have practical exemples/material/tutorial on how to design a PLL starting from these parameters, please share it. I need just an elaborated exemple highligthing the steps of the PLL coefficients determination for the internal compoent (VCO, PFD,..) with mathematic formula using a specification.

Thanks a lot.

pll specification design

1. Phase differeince between o/p and input clocks

2. Jitter of output clock

pll specification

Thanks adsraj

For the point 2 you mean that I have to fix the maximum jitter amount. But how to estimate it. Is there any standard that suggest some ratios for exemple Jitter=0.25*Period ?

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