PLI - designing a test bench in C

[Joyee]

Now, I would like to compose the testbench in C, however, my design is composed by Verilog. Therefore, who knows how to connect them together in the simulation? Does it need PLI? Additionally, who could kindly explain PLI in details?

Thanks in advance!

 

[alledauser]

As far as i know, you need to compose your testbench in verilog. However, you can code models in C, and bind them to the your simulator using PLI. PLI is defined in I*EE verilog std. You can also find lots of online resources and coding examples. Just try a simple search.
regards

 

[Joyee]

Yes, I know. Did you try FPGA Advantage? I just want to compose the tester in C. And I will connect the tester and the UUT(Unit under Test). The whole entity should be called TEST BENCH, right? Therefore, I think your method is right.

Thank you!!

 

[CatKing]

Check the documents of M0d*lSim, you will find a lot of PLI references