PLECS: OP Amp not regulating

[CataM]

Hello everyone,

I have a PSFB converter done in PLECS from Plexim but I can not make it work, even though theoretically looks good.
I can not see any mistake in my implementation, so I need someone else to look at it.

The problem is that the voltage feedback implemented by the Op-Amp is not regulating i.e. it sets the "control signal" for the CPM controller so high, that the current never reaches it and hence the SR flip flop never resets => never switches the bridge leg.
In other words, seems like the converter operates in "open loop".

OP Amp output --> scope 5, it is so high that it can not regulate the converter.
I simply can not see why it does not work.

Output voltage should be 12 V.
"Inverted Biflop" subsystem --> implements the dead time between MOSFETs in the same leg.

Find attached the PLECS schematic. If you need any additional information, just ask, I will kindly provide.

Any comment is highly appreciated !

 

[CataM]

I made a few changes and now seems to work. It gives the correct steady state values, but transient is weird.

*Got rid of secondary and ternary leakage inductances
*Replaced SR FETs with diodes
*Need to add SOFT-START circuitry, otherwise it does not work <-- this is very weird

Now I am doubting this circuit because of those weird things... the output voltage transient (see SCOPE), does not look "trustworthy" in my eyes.


I am open to any recommendations/opinions/changes.

 

[FvM]

The fact that diode rectifiers make the circuit work suggests wrong gate signal patterns respectively wrong logic.

How did you design the control logic? In which sense does it look "theoretical good"? I would appreciate a diagram of expected switch states and circuit currents.

 

[CataM]

The fact that diode rectifiers make the circuit work suggests wrong gate signal patterns respectively wrong logic.

It does not work only by adding diodes. Also needed to add SOFT-START circuitry.

In which sense does it look "theoretical good"?

Because I am simulating an already working hardware prototype, in order to check my implementation in PLECS. The hardware prototype is this and also gives all calculated parameters.
Check that all parameters in my simulation, are exactly the same as in the referenced design.

I would appreciate a diagram of expected switch states and circuit currents.

Waveforms I am basing myself are those from UCC28950 datasheet.

Circuit currents:
Figure 46 (page 36) along with equations in the referenced design note.

Expected switch states:

Figure 46 (page 36) --> shows that QC & QD are the leading leg (leading leg= makes the Active to Passive transition).
This means that QC & QD signals swap (i.e. one goes HIGH while the other goes LOW) when the Current+Artificial ramp>Control Voltage ("Vc" in my schematic) (this is also shown in figure 2 at page 10: when Ramp intersects PWM => QD and QC swap) => which resets the SR flip flop => /Q of SR flip flop is the CLOCK for the QD and QC signal generator. I will get to that in detail below.

Figure 2 (page 10) also shows that every clock signal => QA & QB swap => CLK is the clock for the QA & QB signal generator. I will detail the generation of that signals below.

Generation of QA,QB,QC,QD signals (everything is the same, but with different clock):
JK flip flop: JK tied together with 1 => changes the signal every time its associated clock is rising'edged.

Inverted Biflop: provides pulses (see its subsystem) with time length = dead time. In this example, please see inside that it is exactly 346ns as eq (122) at page 19 of the ref design suggests.
The PLECS "Monoflop" provides a HIGH pulse, so it needs to be inverted in order to "inhibit" the AND gate for providing a HIGH pulse. It is "inhibited" for the "dead time" required.

For example, when "Q" of goes from 0 to 1 => QC goes to HIGH after "dead time" and QD goes to LOW after dead time.
When "Q" goes from 1 to 0, happens the opposite.

Logic for the SR FETs:
Looking at figure 2 (page 10) of datasheet:
QE --> goes to HIGH (i.e. SET) when QC goes HIGH. It goes LOW (i.e. RESET) when QA goes HIGH (or when QB goes low but that requires an extra NOT gate).
QF --> SET via QD and RESET via QB.

 

[CataM]

Controlling the SOFT-START via controlling the reference voltage, gives better transient.



However, I still do not understand why it does not work when starting directly using the steady state reference for the OP Amp. In other words, without soft-start, it does not work. The OP Amp output voltage goes "crazy".