You'll find a clear timing digram of "External Data Memory Write Cycle" in 89C51 hardware description. Data is put on P0 during nWR low, for about 6 clock cycles.
But how do yout want to latch the data in the second 8051? It has no bus device interface or input capture feature. The idea simply doesn't work.
You can of course set the data statically at P0, inform the other processor by an additional port signal about pending data, read it some time later, possibly set an acknowledge signal by the other processor, etc.