Nikhil Motiani
Newbie level 3
Task is to design a folded cascode with single ended output[Differential amplifier + common gate stage]
Conditions required are:
Technology TSMC 180nm technology*
VDD 3.3
CL ≥ 500fF
Current mirror ratios ≤ 20
Power Dissipation ≤ 3mW
DC Gain ≥ 80 dB
UGB ≥ 600 MHz
Phase margin ≈ 55 degree
CMRR ≥120dB
PSRR ≥ 100dB
I set up the bias circuit, along with the schematic with all mosfets in saturation. Also i got gain 95dB but the problem is to set the UGB and Phasemargin simultaneously... Please help...
Conditions required are:
Technology TSMC 180nm technology*
VDD 3.3
CL ≥ 500fF
Current mirror ratios ≤ 20
Power Dissipation ≤ 3mW
DC Gain ≥ 80 dB
UGB ≥ 600 MHz
Phase margin ≈ 55 degree
CMRR ≥120dB
PSRR ≥ 100dB
I set up the bias circuit, along with the schematic with all mosfets in saturation. Also i got gain 95dB but the problem is to set the UGB and Phasemargin simultaneously... Please help...