Please Help on These Interview Questions

[Trader_Joe]

Hello there,

I just wanted to confirm my anwser of the following interview questions.


#13. The current verus Vin curve both are zero at Vin = 0 and Vin =5 and increases gradually from both ends to reach the max value when both transistors are at SAT. The value of Vin = VOD1(min) + VOD2(Min) ~ .3V + 1.3V ~ 1.6V when the max current occurs.

Note: VOD = overdrive voltage = Vgs - Vt

#14

When Vin = 5V,
Vo1 = Vdd - Vtn
Vo2 = Vdd - abs(Vtp)

When Vin = 3V,
Vo1 = Vo2 = 5V

When Vin = 2.5V,
Vo1 = Vo2 = 5V

When Vin = 0V,
Vo1 = Vo2 = 0V


Thank you for your comments,

Joe

 

[safwatonline]

14- in NMOS the Vout cannot exceed Vin-Vth or the MOS will be OFF , while in PMOS the MOS will charge out till Vout=Vdd(of course this dont happen when Vin=5 where the MOS is off).
Vin =5 >>> (Vo1=4.3) ,(Vo2=0)
Vin=3 >>> (Vo1=2.3), (Vo2=5)
Vin=2.5>> (Vo1=1.8),(Vo2=5)
Vin=0>>> (Vo1=0), (Vo2=5)
;Vth=0.7V

 

[Vamsi Mocherla]

Dear Trader_Joe,

#13. I do not see any reason why the current should be zero, when Vin = 5V because both the transistors will be in saturation happily. The current kind of remains constant till the top transistor is ON, because the bottom transistor acts as the current source. The current will start falling and goes to zero when the output voltage falls below the overdrive voltage of the bottom transistor.

#14. Remember one of the transistors is a PMOS and the other an NMOS. Hence at no time, except when the voltage is near VDD/2(assuming all the other ascpects are matched), will have the same response.

I hope that the answers help

 

[safwatonline]

hello vamsi,
about q-13, why the current will be zero when Vout<Veffdown transistor, i THINK that u may look at this crcuit as a NMOS used in transmission gate , so the output voltage will be discharged till zero , i.e. current will be zero when the output voltage is zero.
regards

 

[Trader_Joe]

Thank you for your responses and comments!

It can show how much I forgot ever since I finished those courses!

For #13, my reason the current =0 when Vin = 5 is that the middle point between top and the bottom transistor is at ~ 2.5V (I assume both transistors are the same devices. They have the same resistance. Therefore, by voltage divider, the voltage at the middle node is half of the Vin) If I am correct up to this point, which would lead the top transistor to OFF state since Vgs < Vtn. And by KCL, at any node, the sum of current coming into a node is equal to the sum of coming out of it. So, there is no any current flowing in the bottom transistor either. Any thing wrong?