please help me solve counter issues!

[JacquesKleynhans]

Counter help needed

I get latches in my synplify because the following counter is not created with a clock. I have tried to use the conventional clock with an enable to generate a counter as described here, but it still doesn't work. It works in pre synth but latches up in post synth. Can some please help me solve this issue.

...
signal counter : std_logic_vector(10 downto 0);

...

when state 1 =>
         
counter <= std_logic_vector(unsigned (counter) + 1 );

state_next <=state 2;

when state 2 =>

if unsigned(counter) = 1057 then

state_next <= state 3;
count <= (others => '0');
else
state_next <= state 2;
end if;

when state 3 =>
state_next <= idle;

or maybe suggest a better way of toggling between states and then when number is reached proceeding to next state. I need to use the scheme to add delays and generate clock for my async nand interface.

kindest regards

 

[Logicdevv]

Re: Counter help needed

Hi,
This is not a good practice to write a counter...
any way try to put begin end after then

when state 2 =>
if unsigned(counter) = 1057 then
begin
state_next <= state 3;
count <= (others => '0');
end
else
state_next <= state 2;
end if;

Cheers,
Logicdevv.co.uk

 

[JacquesKleynhans]

Re: Counter help needed

Nea no luck hey. I know the counter is bad form but I have tried doing it like this but it also doesn't work i realy dont know what to do hmmmmm......

signal count : std_logic_vector(10 downto 0);
signal enable, count_rst : std_logic;

process (mem_clk, enable, rst_low, count_rst)
begin
if rst_low = '0' then
count <= (others => '0');


elsif (rising_edge(mem_clk)) then

if enable = '1' then
count <= std_logic_vector(unsigned (count) + 1 );
end if;

if count_rst = '0' then
count <= (others => '0');
end if;
end if;

when read_4 =>

count_rst <= '0';
enable <= '1';

state_next <= read_5;

when read_5 =>

count_rst <= '1';

if unsigned(count) = 10 then --test sequence
state_next <= read_6;
enable <= '0';
end if;


when read_6 =>

 

[shitansh]

Re: Counter help needed

Hi,

make counter in seperate synchronous output logic block of FSM. That is best for your application.

HTH
--
Shitansh Vaghela