Please help me of synthesised code simulation

[yanzixuan]

Hi All, I designed a counter ,and set clock constraint as follow:
create_clock -period 8 -waveform {0 4} [get_ports clk]
do compile and get the synthesised file for simulation.
the timing report as follow([all_registers])

Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
main_cnt_reg[0]/CK (DFFRHQX1) 0.00 0.00 r
main_cnt_reg[0]/Q (DFFRHQX1) 0.27 0.27 r
add_18/A[0] (main_cnt_DW01_inc_1) 0.00 0.27 r
add_18/U1_1_1/CO (ADDHXL) 0.13 0.40 r
add_18/U1_1_2/CO (ADDHXL) 0.12 0.52 r
add_18/U1_1_3/CO (ADDHXL) 0.12 0.65 r
add_18/U1_1_4/CO (ADDHXL) 0.12 0.77 r
add_18/U1_1_5/CO (ADDHXL) 0.12 0.90 r
add_18/U1_1_6/CO (ADDHXL) 0.12 1.02 r
add_18/U1_1_7/CO (ADDHXL) 0.12 1.15 r
add_18/U1_1_8/CO (ADDHXL) 0.12 1.27 r
add_18/U1_1_9/CO (ADDHXL) 0.12 1.39 r
add_18/U2/Y (XOR2X1) 0.12 1.51 f
add_18/SUM[10] (main_cnt_DW01_inc_1) 0.00 1.51 f
main_cnt_reg[10]/D (DFFRHQX1) 0.00 1.51 f
data arrival time 1.51

clock clk (rise edge) 8.00 8.00
clock network delay (ideal) 0.00 8.00
main_cnt_reg[10]/CK (DFFRHQX1) 0.00 8.00 r
library setup time -0.21 7.79
data required time 7.79
--------------------------------------------------------------------------
data required time 7.79
data arrival time -1.51
--------------------------------------------------------------------------
slack (MET) 6.27


but when I do the simulation, the wave is no correct:


if I slowdown the frequency, the waveform is right.
so it's strange for me. if the design pass the timing constraint, how could this error be possible.
Any one can help? BOW~~

 

[oratie]

Did you back annotate timing for simulation (using SDF file)?

 

[yanzixuan]

no. so I add sdf information, it's right now.
Thank you.
But I still wonder, why? I mean, the sdf just increase the net delay. whit out this, the timing performance should be better.
bow

 

[oratie]

Maybe, the behavioral models of the gates have big default delay? I don't remember the syntax of this default delay, but it is possible reason.

 

[poluekt]

Perhaps, for simulation without sdf annotation is used timing parameters equal timeunit (or timeprecision, i don't remember exactly) value.
Сould you please post the massages about violations.

 

[yanzixuan]

Hi poluekt, thank you for your replay ,I had used the command: report_constaint -all_violators
and got such message:
the design has no violated constraints

 

[shitansh]

In gate level simulation you have to take care about trigger you your stimulus on proper time.

Most of time improper trigger of reset will cause problem in you gate level simulation, while in you RTL same test-bench will work. For you if you are reducing clock frequency you are getting proper wave forms clearly indicates that there is improper trigger of your signals in test-bench.

Some tips are below.

(1) In your test bench for reset use reset synchronizer, and then use output of your reset synchronizer as input to DUT. So that there is no recovery or removal violation in your get level simulation.
refer reply in this post for help: https://www.edaboard.com/threads/224800/#post959860

(2) Trigger all other input of your DUT from test-bench on neg-edge flip-flop. so that there will not be any setup and hold violations in your get level simulation.