Please help me. In Vivado program, I have to write the FIFO memory in VHDL language. Photo below is my homework please help me

[barmayon]

The FULL flag will be a warning: When the memory is completely full, the Full flag will come to logic 1 and inform the output that the memory is completely full. It will not accept the PUSH command.
-EMPTY will have a flag warning: When the memory is completely empty, the Empty flag will come to logic 1 and inform the output that the memory is completely empty. It will not accept the POP command.
- Among PUSH, POP and SWP commands, POP will have 1st priority and PUSH will have 2nd priority. In other words, if more than one command comes, POP will be processed first and then PUSH will be processed.
The -RST command will take precedence over all commands.
-NOPOP will be a flag warning. If the POP command cannot be executed for any reason, the NOPOP flag warning will be output and the warning signal will be transmitted to the output.
-NOPUSH flag stimulus. If the PUSH command cannot be executed for any reason, the warning signal will be sent to the output with the NOPUSH flag warning.
Please help me. In Vivado program, I have to write the FIFO memory in VHDL language. Photo below is my homework please help me

 

[barry]

Use a state machine. Beyond that, my fee is US$250/hour for design work.

 

[ads-ee]

You and cetu must be in the same class together, and obviously the class must be poorly taught given both of you are here asking for help to design their FIFO homework for them.

If you want to get a tutorial on FIFO design then you can always search for "cummings fifo1" using a search engine. Ignore the other paper that has FIFO2 in it as that one suffers from potential issues.