please help me in the following vhdl program

[KAVINKUMAR_A]

\\\ prefix of slice name must be an array
\\\ vhdl compiler existing
***** i got this two error . i dont know how to solve it.
***** i want to multiply an 8 bit number with 0.1(decimal number)

please help me

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Code VHDL - [expand]
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library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;
entity mult is  
  port(A : in std_logic_vector(7 downto 0);  
      B : in std_logic_vector(7 downto 0);  
      RES : out std_logic_vector(15 downto 0));  
end mult;  
architecture archi of mult is
signal y : std_logic_vector(7 downto 0);
signal c : real;
 
  begin 
    
     y <=(CONV_INTEGER(c(7 downto 0))); 
    RES <= A * y;  
end archi; 
 
 
data <= mem_data(CONV_INTEGER(addr(15 downto 0)))

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[TrickyDicky]

A real type is not a bit wise type. It is also not suitable for synthesisable designs. So just forget about real types now.

Read up on fixdd point.

 

[KAVINKUMAR_A]

sir .. i cant get your points.. i want to multiply an eight bit number with a decimal value 0.1 ... how can i multiply.. how to alter the program to get a desirable output??

 

[TrickyDicky]

if you really want to use floating point, you will have to use the floating point cores from your vendor.

But I highly suggest you read up on fixed point notation. It is essentially an integer multiplcation with an offset.

Either way, you cannot use the real type in VHDL for synthesisable designs.

 

[KAVINKUMAR_A]

sir.. i studied about fixed points . while i m using the fixed point packages in altera quartus 2 modelsim 9.1, there was an error.. how to overcome from this error??

\\library ieee_proposed not found

i searched through online but i cant get cleared from the above error..

help me sir

 

[TrickyDicky]

you need to map the library into modelsim. You need to make sure the library is compiled in modelsim first, and then you can map it either via the gui, or with the command:

vmap ieee_proposed /<path to ieee_proposed>/

But if you get a newer version of modelsim, this package is included as part of the ieee library. The fixed point packages are part of the VHDL 2008 standard, and can be included like:

use ieee.fixed_pkg.all;