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Please help me debug my vhdl code of 4 bit ALU

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RollingEEE

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4 bit alu vhdl

This code is suppose to be vhdl for a 4 bit ALU

Code:
library ieee;
use ieee.std_logic_1164.all;
use work.all;

entity normalalu is
	port (A, B: in std_ulogic_vector(0 to 3);
		  O   : out std_ulogic_vector(0 to 4);
		  S	  : in std_ulogic_vector (0 to 1));
end normalalu;
		  
architecture behavior of normalalu is
begin
	reg:process(A, B, S)
	variable Q: std_ulogic_vector(0 to 4);
	begin
		if S = "00" then
			O(0 to 4)<= A(0 to 3) + B(0 to 3);
		elsif S = "01" then
			O(0 to 4)<= A(0 to 3) - B(0 to 3);
		elsif S = "10" then
			O(0 to 4)<= A(0 to 3) and B(0 to 3);
		else
			O(0 to 4)<= A(0 to 3) or B(0 to 3);
		end if;
	end process;
end behavior;

QuartusII gives error saying that
Error (10327): VHDL error at normalalu.vhd(17): can't determine definition of operator ""+"" -- found 0 possible definitions[/code]

Please help
 

jeremylbt

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vhdl code for 4 bit alu

I believe you have missed out "use IEEE.numeric_std.all;"

On another note, your code can be trimmed as follows:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.all;

entity normalalu is
port (A, B: in std_ulogic_vector(0 to 3);
O : out std_ulogic_vector(0 to 4);
S : in std_ulogic_vector (0 to 1));
end normalalu;

architecture behavior of normalalu is
begin
reg:process(A, B, S)
begin
if S = "00" then
O <= A + B;
elsif S = "01" then
O <= A - B;
elsif S = "10" then
O<= A and B;
else
O <= A or B;
end if;
end process;
end behavior;

Your variable Q is not necessary.
 

vlsi_whiz

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vhdl code for alu

You're getting this error cause you haven't declared the IEEE math libraries where these functions (+,-,etc) are found. You have to use these libraries. I think the math libraries are obsolete..so use the Numeric_Std library. This will solve the error.
 

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