please help me about look up table

[alierossi]

hi...
i am doing my project about look up table...
i have 4000 data with value like this

data no > value

1 > 0.3
2 > 0.4
3 > 0.8
4 > 0.3
5 > 0.5
6 > 0.6
7 > 0.2
8 > 0.125
9 > 0.35
: > :
: > :
4000 > :

how can i embedded this value in fpga and fpga can produce this value as output. so that i can run this value to hardware. my hardware actually flexible manipulator.
please help me. i am quite new in fpga and vhdl.

 

[Rajppd]

are you talking of analog data values? If yes, you must segregate them to digital logic. after that do a truth table logic and proceed to program. if your data is static, there would be no complication. if it is going to be dynamic, your software should be structured accordingly. hope this helps.

 

[alierossi]

yes analog data value...
sooryy i dont understand what are u mentioned...can give more explaination
and example to me... please help me...

 

[Rajppd]

you can try to read some material on ADC (Analog to Digital Conversion). Bear in mind that TTL, CMOS all have their own digital level standards. You must see what type of hardware you are using here.

 

[alierossi]

can u give me an example...
i actually use xilinx spartan 3e...
please help me...

 

[FvM]

Rajppd's anaswer was refering to the fact, that digital logic can't directly represent a signal like 0.125. The most basic question is: How is the output of your design interfaced to the outer world? To you intend to drive an anlog signal (e.g. a 0 to 10V control voltage) or a digital signal (e.g. send a command string to the manipulator controller via RS232). This question hasn't to do with look up tables, it's about your general project setup. We can't know it.

Digital logic can represent analog signals as different kinds of numbers. Standard FPGA libraries are mostly using integer (signed or unsigned) numbers. If you decide, that 1/4095 respectively 12 Bit resolution is sufficient to represent your signal, you can use a 4000 word x 12 Bit ROM in your design to build the look up table.

 

[alierossi]

any example of the vhdl code for this rom?

 

[FvM]

Xilinx users should tell. With Altera Q.uartus, internal ROM can be "inferred" from an initialized constant array or a case structure.
The best method depends on where you get the data for your table. If it's supplied from an external data file, e.g. a *.hex file, a
ROM IP function ("MegaFunction") referencing the data file would be instatianted. If the data can be described by a simple generator
algorithm, e.g. a sine table, it can be implemented as an initialized VHDL data structure.

I would expect th Xilinx tool documents to tell how to.

 

[alierossi]

xilinx tool documentation did not help...
can anyone tell me ...
please...

 

[rberek]

The easiest way for you to generate a ROM would be to use Xilinx's Coregen tool, which is a part of the ISE design suite. It will create the VHDL code for you.

Xilinx uses .COE files to indicate the initial value of a memory. Examples of COE files can be found in the $XILINX/coregen/data directory, where $XILINX is the location of your Xilinx ISE installation. Basically, your COE file is going to have 4000 hex numbers representing the contents of each ROM row.

Coregen will ask you which COE file it should use when it is creating your ROM.

As others have pointed out, your challenge will be how you intend to represent floating point numbers in hexadecimal format.

r.b.

 

[alierossi]

please help me. any advice?

 

[rberek]

What additional advice do you need?

Did you build a ROM using Coregen yet? Did you try to create a COE file? Did you simulate it to see if it was giving the correct output? Did you do any work on determining your requirements as to the type and format of data you'll be storing in the ROM?

Without knowing what you've done so far, how can we advise you? Be specific.