Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Please help me about guard-ring issues

Status
Not open for further replies.

rf_usn

Newbie level 4
Joined
May 11, 2007
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,322
Hi all,

I am now designing RF part in the SoC. We all know that the guarding is needed for noise isolation. I have found some papers discussing about the effect of guard ring's width on the isolation. Ex. in the paper "On the P+ guard ring sizing strategy to shield against substrate noise" published in RFIC symposium in 2007, they say that starting from a guarding width above 16 um, the isolation saturates with the guard ring width. Now, let's say that we have 2 blocks that need to be isolated by guard ring; then my question is what is the typical distance between two blocks? Can anyone show me the reference about that? Thank you very much in advance.

Best regards,

rf_usn.
 

I don't know how others but in my experience the bes "shield" is the distance. In critical circuitry like I usualy do "tripple" guardring (P+ / N+ / P+) and try to keep as much of "empty" substrate without any active device or guardring with thick oxide as possible. Since die is limited I am trying to get spacing of 50um - which seems to isolate quite well.
 

Thanks Teddy very much.
 

hi k_90,

If you want, I can send you buy email.

Added after 5 minutes:

hi k_90,

I am trying to upload that paper here.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top