Please help asynchronous combination lock

[Yigit Bireroglu]

I have a project that I have to turn in tomorrow. I am having some difficulties. Its my first year at University, I would be really grateful for some help. Here’s the question,

This combination lock has a minimum sequence of four two-bit input symbols as the combination and appears to the user as if it is an asynchronous circuit. Actually, it is a synchronous circuit with a fast clock and synchronization of the user inputs. For a given input combination, the circuit goes to a state and cycles there until the input changes to a new symbol; thus, the combination cannot contain consecutive appearances of the same symbol. The lock is locked by using an asynchronous RESET.

It will be designed in VHDL Schematics.
Thank you very much

 

[mail4idle2]

Please can you be more elaborate on the question.

 

[BradtheRad]

Occasionally this question comes up here. Look at the list of threads on related topics (bottom of this page). Clicking those might lead you to information that will help with your project.

 

[Yigit Bireroglu]

Please can you be more elaborate on the question.

This is all the info I have as well, but maybe this can help

Specify a simple digital system,
Separate the system into one or more datapaths and controls,
Design the datapath(s) for the system,
Design the control(s) for the system,
Integrate the datapath(s) and control(s) into an overall system,
Devise a thorough test for the system,
Implement the system using Xilinx Foundation Software, and
Test and debug the system.

 

[Yigit Bireroglu]

I had in mind to have four signal inputs, each one of them going into 2x1 MUX with themselves, and the output of the MUXs going into four flip-flops, and the output of the flip-flops going into an AND logic gate according to the desired combination. But I just wanted to get some more ideas.

 

[ads_ee]

Unless there is a guaranteed way of applying the 2-bit code word to the design synchronously to the clock then there will be issues as the input code is, I assume, coming from switches or something external to the FPGA. Simply synchronizing the input code won't work as you may capture one bit and miss the other till the next clock.

You may want to consider having the input code word "switches" and a "set_the_code" switch. This incidentally would make the design more robust as you can now have the same code word used in successive positions. So you could then have 00 01 01 11 as a valid unlock code. The set_the_code "pulse" (you'll have to debounce a switch used this way) will also enable the FSM to transition through the "lock". Your RESET should also force the unlock FSM to return to an IDLE state, which incidentally could be the LOCKED state.

Hope that gives you something to think about, but you're likely already late with your project. :-(

 

[Yigit Bireroglu]

I have completed the project, thank you very much to all who paid attention. Have a nice day