kurukuru
Junior Member level 1
The attachment is timing diagram of DAC codec IC PCM3008 (16 bit serial) that I would like to interface using FPGA.
As in the diagram I have already create LRCK (which is sampling freq. 32kHz) and BCK (which is bit shifting freq. 512kHz) by divide my clock input.
The problem is I don't know how to detect when to start shif my data from first bit to last bit respectively since LRCK and BCK is freely run from the start.
Would anyone guide me by provide me some guide? VHDL code also appreciate as well as others suggests.
Thank you
As in the diagram I have already create LRCK (which is sampling freq. 32kHz) and BCK (which is bit shifting freq. 512kHz) by divide my clock input.
The problem is I don't know how to detect when to start shif my data from first bit to last bit respectively since LRCK and BCK is freely run from the start.
Would anyone guide me by provide me some guide? VHDL code also appreciate as well as others suggests.
Thank you