Placing IO Pads in 90 nm

[Debdut]

Hello,
I'm designing in umc 90 nm technology using Cadence Virtuoso.
Finally I may have to do Layout and maybe subsequent chip design.
I have some idea about layout, however I do not know how to place pad rings in the final design in umc 90 nm. I have searched the internet but could not get a clear idea.
Are there any tutorials available which I can follow? Are there any companies in India doing layout in 90 nm who provide training on the topic?
Please help!

 

[erikl]

Your 90nm PDK should give you hints; possibly it could contain an I/Opad library incl. layouts. See here various IOpad styles (from a TSMC lib):

 

[Debdut]

I cannot understand them. Are there any references?
I searched in the documents related to umc 90nm that were downloaded when the designkits were download from europractice.
Unfortunately I did not find any data related to the pads. There is only one pad in umc90mm library that is PAD_BOAC_RF. I did not find anything related to that either. :-(