place and roout section is fialed

[electronical]

Hello,
in may vhdl program,I have several matrix.
when I syn it with ISE, the process in the place and rout section is failed with no error. when I decrease the size of matrix(as 1/4) the program is synthesis.
why place and rout is fialed ?

 

[barry]

can you tell us what you mean by failed? Did you get an error message? what is it? My guess is you require more resources than are available on your FPGA, that's why it compiled ok when you reduced your matrices.

 

[electronical]

thank you, i think my code require more resources. I reduced the memories and process success.
but I cant understand why it failed with no errors.
when MAP was successfully synthesized, it means there is enough resource to use this IC for code?

 

[barry]

I'd be pretty surprised if you didn't get SOME message about being over-mapped. go back and look at the reports. When you say 'it failed' doesn't that mean there's an error?

 

[electronical]

I sent you the place and route report.
no error is occured.I use virtex 6, when use Xc67hx380T, the place and route is failed. when use Xc67LX760 ,it is fialed.

 

[barry]

There is nothing to indicate it failed in yout report. Why do you say it failed? If there is no error, then there is no failure, right?

 

[electronical]

in report was write, the RAR is done.
but report in console :
PAR done!

Process "Place & Route" failed

 

[barry]

It failed because timing was not met. It says "2 constraints not met"