Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
A pipelined architecture produces an output more regularly than a regular architecture.
A regular architecture will produce a single output say every 10 clocks. But if it pipelined it can produce an output every clock from the 10th clock onwards. From the 10th clock onwards it can accept a new input every clock and produce a new output every clock.
I don't understand this... As far as I know, pipeline comes to solve timing problems... So that a single operation might be divided to several sub-operations, each one of which is performed during a single pipeline stage...
Yes. You are right. Pipelining also solves timing problems by doing what you say in your previous post.
Ok. Ignore my previous post. I now understand that by saying "faster" you mean the design can work at a higher frequency.
So in pipelining long combinational paths are cut down by inserting registers in between them. This reduces the combi delay and thus enables us to achieve a better timing performance. But it adds several clock cycles in latency which you have to live with.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
