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A pipelined architecture produces an output more regularly than a regular architecture.
A regular architecture will produce a single output say every 10 clocks. But if it pipelined it can produce an output every clock from the 10th clock onwards. From the 10th clock onwards it can accept a new input every clock and produce a new output every clock.
I don't understand this... As far as I know, pipeline comes to solve timing problems... So that a single operation might be divided to several sub-operations, each one of which is performed during a single pipeline stage...
Yes. You are right. Pipelining also solves timing problems by doing what you say in your previous post.
Ok. Ignore my previous post. I now understand that by saying "faster" you mean the design can work at a higher frequency.
So in pipelining long combinational paths are cut down by inserting registers in between them. This reduces the combi delay and thus enables us to achieve a better timing performance. But it adds several clock cycles in latency which you have to live with.