Pipeline with HaRvard architecture

[Jiadong Yao]

Pipeline with Harvard architecture

Hi, when i was taking the µp class, our professor said something that seems not correct.



He said the architecture has some problem. As you can see in the picture, below the register S2, he insisted that there should be one more register.
In other words, between the MDR and Registers, there is one more register.

I dont believe it. Since the architecture comes from harvard, I don't think Harvard will make such a small mistake.

What do you think?

 

[MSBR]

Well, in my opinion, your professor seems to be right. The additional register (shown in red) in the second figure will ensure that there are same number of cycles from Register to data memory. If that register is omitted. then there would be a mismatch in pipeline stages.

But yes, it is also important to note that how does this architecture work. For example, if the working ensures that the register data is latched until the respective address of memory becomes available, then the first figure would work fine either. But if the design is fully pipelined, then you can see that data from registers will become available one cycle earlier than its respective address (Structural Hazard).

I hope that it makes the point clear.

Thanks.
MSBR

 

[ashugtiwari]

Im not completely sure but It depends on what architecture u r studying. If architecture has this arrangement then it is there but if its some FPGA VHDL code then the register is not required there since in most of RISC, the load and store from and to data memory happens in single clock and this can be buffered to keep sync. But if u double buffer it, i think the single cycle execution may not be possible, it will take one more clock cycle to go from first buffer to second buffer.

Hope that helps.