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Pipeline adc gain error

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predator89

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Hello Everyone,
I am designing 12 bit pipelined ADC. I am facing problem to get the accurate gain of 2 from the designed MDAC when I use the capacitors from technology library.
When I replace the CI and CF capacitors with the ideal caps I get accurate 2 gain when I check the residual output of each stage, also INL of +-0.5LSB and also no PVT variation.

Can anyone suggest me possible method to get accurate gain from MDAC.

Any help will be welcome.
Thanks in advance.

Cheers
 

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