Pipeline ADC dynamic comparator latch signal

[iamxo]

pipeline adc

Let me say the Sha and first Mdac, at the beginning, I set the comparator latch signal at almost the end of hold time of Sha ( Say, 10ns clock cycle, about 5ns for hold, but non-overlap clock actually), so my latch signal rise to VDD at 4ns before the end of the hold time ( that is, 1ns width for latch signal ).

However, in simulation, I find that when the latch signal goes high, the comparator kick-back noise degrades my Sha settling time, that is in my 5ns hold time, the Sha can not settle to the desired value.

So, my query is " May I let the latch signal comes earlier? Such as at the middle of the Sha hold time when the Sha almost settle to the desired value but not that accurate.

(May you all have got me) Thanks very much..

 

[iamxo]

comprator for pipelin adc

Or, let say when the latch signal should go high during the hold time?

 

[eecs4ever]

comparator in pipeline adc

Yes, you can latch the comparator earlier. Your output from your Sha at the time will not be as accurate, but since you are probably using redundancy, you can tolerate some error in your flash ADC.

OR

you can add a separate path for the your flash ADC. Sample the signal on the sha and for your flash adc at the same time in separate circuits. And then you can enable the latch afterwards at the beginning of the hold period. This eliminates the kick back problem since they are operating in isolated circuits. But the timing difference will introduce an error , but should be fine if you are operating < ~200MS/s .

Or, you can make a lower powered replica sha. just have 2 Shas running in parallel. 1 for the main signal path, 1 for dynamic comparator latch. Now the kick back wont affect the main signal path. For the sha that drives the dynamic latch can be made much smaller and use less power.

Added after 3 minutes:

"when the latch signal should go high during the hold time?

"
You should determine how accurately you want the Sha output to settle. And calculate this time based on the settling time of your SHA. You can tolerate some error if use redundancy (like the 1.5b/stage algorithm).

 

[iamxo]

comparator latch

Thank you so much, guy.
Now, I just use early latch signal to my sub-ADC, and the error caused by kick-back noise has almost no effect on my Sha.

However, are these methods common in commercial pipeline ADC design? Such as early latch signal, parallel path?