Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Pipeline ADC Digital Correction Algorithm

Status
Not open for further replies.

hspice

Newbie level 5
Joined
Jul 10, 2004
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
71
pipeline adc digital correction

Dear all:



I'm designing a 12bit piepline adc (very conventional one). it's based on 1.5bit/stage + 3bit (last stage). In some papers and products specs, there are more than enough stages over all, say: 12 1.5bit stages and one 3bit stages. I'm just wondering what algorithm in this case, after RSD digital correction, there will be 15bit resolution and discard last 3 stages?! What's benefit behind this "luxurious" correction?

Appreciate your help.



Vincent
 

rsd correction for adc algorithmic

Vincent,

IMO, the more the redundant bits, the larger comparator offset voltage can be tolerated. Maybe that's the reason.

Stan
 

rsd digital correction algorithm

more the redundant bits, the larger comparator offset voltage can be tolerated?
what is the reason?
 

pipeline flash adc, digital error correction

who can give some meterials of digital calibration?
 

Hi hspice,
I wonder why should anybody use a 3-bit flash ADC as the last stage and after digital error correction, remove three last stages. This may even results in some problems. please explain your problem in more details and/or send the particular case.

Regards,
EZT
 

Hi fellows

This thread interests me very much.. since my final school project it's projecting ADC pipeline (with Flash arquitecture) i want to know if you fellows can give a clue how i can make the digital correction algorithm when i'm joining diferent types of arquitecture, i.e i want to project a pipeline that have more than one arquitecture, in my case i have the 1.5 bit, 2.5 bit and 3.5 bit flash arquitecture with the 2 bit flash as the last stage like normaly, but instead of making a pipeline of a single arquitecture i want to join them aleatory form, or as i want and still have a correct pipeline output...

My question is what i have to have in consideration to implement that? What changes i have to do to the "weight" digital correction algorithm ? I have to find other algorithm?

At last, it is possible at all?

thanks

Pipe
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top