hspice
Newbie level 5

pipeline adc digital correction
Dear all:
I'm designing a 12bit piepline adc (very conventional one). it's based on 1.5bit/stage + 3bit (last stage). In some papers and products specs, there are more than enough stages over all, say: 12 1.5bit stages and one 3bit stages. I'm just wondering what algorithm in this case, after RSD digital correction, there will be 15bit resolution and discard last 3 stages?! What's benefit behind this "luxurious" correction?
Appreciate your help.
Vincent
Dear all:
I'm designing a 12bit piepline adc (very conventional one). it's based on 1.5bit/stage + 3bit (last stage). In some papers and products specs, there are more than enough stages over all, say: 12 1.5bit stages and one 3bit stages. I'm just wondering what algorithm in this case, after RSD digital correction, there will be 15bit resolution and discard last 3 stages?! What's benefit behind this "luxurious" correction?
Appreciate your help.
Vincent