Pipeline ADC design's puzzle

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GaryHan

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I am designing a 8bit 100MHz Pipeline ADC, and the result puzzled me.
The structure is 1.5bit/stage *5 + 3bit/last stage. The result is that 1Lsb is always wrong. Can someone give some advise ? Or point some key notation?
Additions: In this design, there are a S/H circuit, gain stage(include OTAs), dynamic Comparator, and bias circuit. How about the key spec of these analog circuit?
Help!!! Thx!!!
 

can u post schematic of ur architecture..description is not very much clear..
 

Can u describe your problem more clearly?
In your design, there are 1.5bit/stage*5 + 3 bit/last stage.
How do you design your digital correction circuit?
As I know, we will need digital correction circuit to correct the result code
of 1.5 bit/stage and ignore the last code.
 

Did you check the output of the last stage's OTA? I had the same problem before and found that the problem came from the last stage.

Good Luck!
 

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